Nowadays, multistandard and software-defined radios are emerging, encouraged by the RF capabilities of scaled CMOS and ultimately striving for cognitive radios. Meanwhile, the mask costs of scaled CMOS rise to dramatic heights. In a search for ways to repay this increased cost, low area RF design in digital CMOS has become a hot research topic.
Broadband amplifiers are commonly used as a low area solution for the integration of LNAs for multistandard receivers, as in R. Bagheri et al., “An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS”, IEEE JSSC, Vol. 41, No. 12, pp. 2860-2876, December 2006. In scaled CMOS technologies, inductor-less designs attain bandwidths above 6 GHz. Their broadband nature however, imposes high linearity demands on both the LNA and at system level. Alternatively, separate narrowband LNAs relax linearity concerns significantly. While this solution allows optimized performance in each band, the area consumption forms a serious drawback. Multiband LNAs (e.g. H. Hashemi, A. Hajimiri, “Concurrent multiband low-noise amplifiers—theory, design and applications”, IEEE Trans. On Microwave Theory and Techniques, Vol. 50, No. 1, Part 2, pp. 288-301, January 2002) offer a compromise between wideband and multiple separate LNAs. Often however, these solutions are limited to two bands, and still bear a relatively large area penalty for a reduced performance.
A broadband LNA circuit is disclosed by Andersson, S. et al. in “Wideband LNA for a Multistandard Wireless Receiver in 0.18 μm CMOS”, European Solid-state Circuits, Piscataway, N.J., USA, IEEE, 16 Sep. 2003, pp. 655-658. The circuit comprises an inductor as part of the load. The frequency band in which the amplifier operates is however determined by an inductor at the input.